This article describes the principle, design and operation of a digital stopwatch circuit. A digital stopwatch can be a circuit displaying the actual time in minutes, hours and seconds or a circuit displaying the number of clock pulses. Here we design the second type wherein the circuit displays count from 0 to 59, representing a 60 second time interval. In other words here the circuit displays the time in seconds only. This is a simple circuit consisting of a 555 timer to produce the clock pulses and two counter ICs to carry out the counting operation.
Digital Stopwatch Circuit Principle:
This circuit is based on the principle of 2 stage counter operation, based on synchronous cascading. The idea is to display clock pulses count from 0 to 59, representing a 60-second time interval. This is done by using a 555 Timer IC connected in a stable mode to produce the clock pulses of 1 second interval each. While the first counter counts from 0 to 9, the second counter starts its counting operation every time the count value of first counter reaches 9. The counter ICs connected in cascading format and each counter output is connected to BCD to 7 segment decoders used to drive the 7 segment displays.
Digital Stopwatch Circuit Diagram:
Digital Stopwatch Circuit Design:
First part of design involves designing the stable multi vibrator arrangement of 555 Timer. Here the required time period is 1 second. With the frequency of output signal given by f = 1.44/ (Ra+Rb) C, we can calculate the values of C, assuming values of Ra and Rb to be around 10K. Here we get a 100uF electrolyte capacitor.
Second part of designing involves connecting the two counters IC – 4510 in synchronous cascading arrangement. This is achieved by connecting the clock pins of the counter ICs to the output of 555 Timer, resulting in parallel clock input signals. The carry out pin of one of the IC is connected to the carry in pin of another IC.
Since our concern is to start the second counter once the first counter reaches the count value of 9, we accomplish this by designing a simple combinations’ logic circuit. Recalling from the counter truth table, for a clock pulse count of 9, the corresponding binary count or status of counter output signal is 1001. In other words for a count of 9, Q1 and Q4 are at high logic signals. Here we are using an AND gate IC 7408 whose inputs are connected to pins Q1 and Q4 of the first counter and output is connected to the U/D pin of second counter.
Here our requirement is to display the clock pulses till count of 60. This can be done by ensuring the second counter resets once the count reaches a value of 5. We achieve again by designing a simple logic circuit consisting of another AND gate IC, whose inputs are connected to pins Q3 and Q2 of the second counter.
The third part involves designing the display circuits. This is done by connecting the outputs of each counter IC to the inputs of BCD to 7 Segment Decoders. The outputs of each Decoder ICs 4511 are connected to the 7 Segment display.
Working of Digital Stopwatch Circuit:
The circuit operation begins once the normally open switch is changed to closed position. The Timer 555 produces high and low signals at frequent intervals, resulting in oscillating signal whose frequency is based on the values of two resistors and the charging capacitor. In other words, the timer 555 IC produces the clock pulses of required time period. This clock signal is fed to the two stage arrangement of BCD counters CD4510. The IC CD4510 consists of four synchronously clocked D- Flip-flops, which are connected together to enable the counting operation. The clock pulses are counted by the two stage synchronous cascaded arrangement of two CD4510 counters. As IC U3 receives the clock pulses, it starts counting from 0 to 9. Once the count reaches 9, the AND gate IC U4A produces a high logic output, which is fed to the U/D pin of IC U2. IC U2 starts the count operation. The IC U2 continues its counting operation and so does the IC U3 every time U3 reaches its end count. However once the IC U2 count reaches count of 6, the reset pin is set to high level by the AND gate U5B. The count is displayed on the 7 segment displays driven by the BCD to 7 segment decoders CD4511. The circuit thus displays the clock pulses from 0 to 60.
Digital Stopwatch Applications:
- This circuit can be used as an indicator at quiz competitions.
Digital Stopwatch Limitations:
- The circuit does not display the actual time, but rather the count of clock pulses.
- The use of digital counter ICs produces a time delay in the whole operation, because of the propagation delay.
- This is a theoretical circuit and may require changes.