Most often seven-segment displays are used to display the digits in digital watches, calculators, clocks, measuring instruments and digital counters, etc. Generally, LCD and LED segments to provide the display output of numerical numbers and characters.

However, to display the characters and numbers (in order to produce the decimal readout), seven-segment displays are most commonly used. Mostly these displays are driven by the output stages of digital ICs (to which the visual indication of the output stages has to be performed) such as latches and decade counters, etc.

But these outputs are in the form of 4-bit binary coded decimal (BCD), and not suitable for directly driving the seven-segment displays.

A display decoder is used to convert a BCD or a binary code into a 7 segment code. It generally has 4 input lines and 7 output lines. Here we design a simple display decoder circuit using logic gates.

Even though commercial BCD to 7 segment decoders is available, designing a display decoder using logic gates may prove to be beneficial from economical as well as a knowledge point of view.

The principle of Display Decoder Circuit

The basic idea involves driving a common cathode 7-segment LED display using a combinational logic circuit.  The logic circuit is designed with 4 inputs and 7 outputs, each representing an input to the display IC. Using Karnough’s map, logic circuitry for each input to the display is designed.

Theory Behind the Circuit:

The first and foremost aspect of this circuit is a decoder. A decoder is a combinational circuit which is used to convert a binary or BCD (Binary Coded Decimal) number to the corresponding decimal number. It can be a simple binary to a decimal decoder or a BCD to 7 segment decoder.

Another relevant section is the combinational logic circuitry. A combinational logic circuit is a system of logic gates consisting of only outputs and inputs. The output of a combinational logic circuit depends only on the present state of the inputs and nothing else. Best examples of such circuits are Encoders and Decoders, Multiplexers and De-multiplexers, Adders, Subtractors etc.

To understand the design and operation of these logic circuits, one needs to have a good knowledge of Boolean algebra and logic gates. For example, few basic Boolean algebra rules to be followed are the complementary law, associative law, De-Morgan’s law etc.

A 7 segment LED display consists of an arrangement of 8 LEDs such that either all the anodes are common or cathodes are common.  A common cathode 7 segment display consists of 8 pins – 7 input pins labeled from ‘a’ to ‘g’ and 8th pin as a common ground pin.

7 Segment Display Decoder Circuit Design

Step 1: The first step of the design involves an analysis of the common cathode 7-segment display.  A 7-segment display consists of an arrangement of LEDs in an ‘H’ form.  A truth table is constructed with a combination of inputs for each decimal number. For example, decimal number 1 would command a combination of b and c (refer to the diagram given below).

Common Cathode 7 –Segment LED

7 Segment LED

Image Resource Link:

Step 2: The second step involves constructing the truth table listing the 7 display input signals, decimal number and corresponding 4 digit binary numbers.

The truth table for the decoder design depends on the type of 7-segment display. As we mentioned above that for a common cathode seven-segment display, the output of decoder or segment driver must be active high in order to glow the segment.

The figure below shows the truth table of a BCD to the seven-segment decoder with a common cathode display. In the truth table, there are 7 different output columns corresponding to each of the 7 segments.

Suppose the column for segment a shows the different combinations for which it is to be illuminated. So ‘a’ is active for the digits 0, 2, 3, 5, 6, 7, 8 and 9.

BCD to common anode 7 segment truth table

From the above truth table, the Boolean expressions of each output functions can be written as

a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)

b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)

c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)

d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)

e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)

f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)

g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)

Step 3: The third step involves constructing the Karnough’s map for each output term and then simplifying them to obtain a logic combination of inputs for each output.

K-Map Simplification

The below figures shows the k-map simplification for the common cathode seven-segment decoder in order to design the combinational circuit.

K-map 1

K-map 2

K-map 3

From the above simplification, we get the output values as

k map simplification

Step 4: The final step involves drawing a combinational logic circuit for each output signal. Once the task was accomplished, a combinational logic circuit can be drawn using 4  inputs (A,B,C,D)and a 7- segment display (a,b,c,d,e,f,g) as output.

BCD to 7-segment Decoder Design Using Basic Gates

Display Decoder Circuit Operation

The circuit operation can be understood through the truth table itself. When all the inputs are connected to low logic, the output of the combinational logic circuit would be so as to drive all the output LEDs except ‘g’ to conduction.  Thus the number 0 will be displayed. A similar operation would take place for all other combinations of the input switches.

Practically BCD to 7 segment decoders are available in form of integrated circuits such as 74LS47.  Apart from regular 4 input pins and 7 output pins, it consists of a lamping test pin used for segment testing, ripple blanking input pin used to blank off zeros in multiple display systems, ripple-blanking output pin used for cascading purposes and a blanking input pin.

Applications of Display Decoder Circuit

  1. This circuit can be modified using timers and counters to display the number of clock pulses.
  2. This circuit can be modified to develop an alphabet display system instead of a decimal number display system.
  3. It can be used as a timer circuit.

Limitations of Display Decoder Circuit

  1. This circuit involves a lot of logic gates and is quite complex.
  2. Timing delay by each logic gate is a matter of concern and this circuit might not produce accurate results when used to display a count of pulses.
  3. This is a theoretical circuit and may require few modifications.


Please enter your comment!
Please enter your name here